The use of Hardware-in-the-Loop (HIL) systems implemented in Field Programmable\nGate Arrays (FPGAs) is constantly increasing because of its advantages compared to traditional\nsimulation techniques. This increase in usage has caused new challenges related to the improvement\nof their performance and features like the number of output channels, while the price of HIL systems\nis diminishing. At present, the use of low-speed Digital-to-Analog Converters (DACs) is starting to\nbe a commercial possibility because of two reasons. One is their lower price and the other is their\nlower pin count, which determines the number and price of the FPGAs that are necessary to handle\nthose DACs. This paper compares four filtering approaches for providing suitable data to low-speed\nDACs, which help to filter high-speed input signals, discarding the need of using expensive highspeed\nDACS, and therefore decreasing the total cost of HIL implementations. Results show that the\nselection of the appropriate filter should be based on the type of the input waveform and the relative\nimportance of the dynamics versus the area.
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